Lots of opinions in this arena. Below are mine. ymmv.

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Haven't really found a proper descripton in case of 2 socket how to pin osds to numa node, only this: https://tracker.ceph.com/projects/ceph/wiki/Tuning_for_All_Flash_Deployments... Tuning for All Flash Deployments - Ceph - Ceph <https://tracker.ceph.com/projects/ceph/wiki/Tuning_for_All_Flash_Deployments#Ceph-Storage-Node-NUMA-Tuning>

A bit dated, note the reference to Jewel and thus XFS / Filestore.

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Redmine tracker.ceph.com Is there anybody have some good how to on this topic?

Wido's presentation from a few years ago re affordable NVMe Ceph may be of interest.

I'm also interested in how to configure NUMA for Ceph.

My sense is that with recent OS and kernel releases (e.g., not CentOS 8) irqbalance does a halfway decent job.

I came across a recent Ceph day NYC talk from Tyler Stachecki (Bloomberg) [1] and a Reddit post [2]. Apparently there is quita a bit of performance to gain when NUMA is optimally configured for Ceph.

My sense is that NUMA is very much a function of what CPUs one is using, and 1S vs 2S / 4S. With 4S servers I've seen people using multiple NICs, multiple HBAs, etc., effectively partitioning into 4x 1S servers. Why not save yourself hassle and just use 1S to begin with? 4+S-capable CPUs cost more and sometimes lag generationally. cf. Mark and Dan's Journey to 1TB/s post, it discusses the impact of inter-socket communication and IOMMU. With EPYCs, one may gain by disabling IOMMU on the kernel commandline, and other tunings including NPS values. Xeons may require less adjustment from defaults. There is growing favor for 1S servers. 2S has been de-facto for years, because CPUs with higher core counts were disproportionally expensive. XCC vs MCC CPU SKUs may matter too. With Emerald Rapids and Genoa, we may be able to afford a desired core/thread count (say, 4-6 vcores/threads per NVMe OSD) with a single socket. Note that 1S servers may have differing RAM population dynamics.

Red Hat documentation (hyper converged infra)

I may be heterodox, but I dislike convergence. ymmv.

suggests to pin the Ceph processes on the CPU with the storage controller / NIC attached [3]. In an all flash system there is not just one storage controller but the NVMe are attached to different PCIe buses spread across the different NUMA nodes.

Look up your server / motherboard specifically. With, say, Dell systems, there are often multiple variants of a model, each with very different PCI-e - NVMe mappings. Especially if there is an antiquated and counterproductive RAID HBA present, the NVMe bays may not be even close to evenly distributed across two sockets.

So what is most optimal there? Does it still make sense to have the Ceph processes bound to the CPU where their respective NVMe resides when the network interface card is attached to another CPU / NUMA node? Or would this just result in more inter NUMA traffic (latency) and negate any possible gains that could have been made?

Is the benefit of NUMA optimization so large that it would make sense to add another NIC to the system, add it to the other NUMA domain and have half the OSDs listen on one nic (IP), and the rest of the OSDs on the other nic (separate IP)?

That sounds like two servers to me. One reason I favor 1S 1U servers for Ceph.

Ceph has an admin command to show the NUMA status that gives the following output for a node called storage1:

ceph osd numa-status OSD HOST NETWORK STORAGE AFFINITY CPUS 0 storage1 - 2 - - 1 storage1 - 2 - - 2 storage1 - 2 - - 3 storage1 - 1 - - 4 storage1 - 1 - - 5 storage1 - 0 - - 6 storage1 - 0 - - 7 storage1 - 0 - - 8 storage1 - 2 - -

But I'm unsure what that means. Because when I look up the numa status for the OSD processes it shows the following:

numactl -s 22579 policy: default preferred node: current physcpubind: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cpubind: 1 2 nodebind: 1 2 membind: 1 2

And its the same for all OSDs (NUMA node 0 / 4 only have CPUs and no memory (AMD EPYC 7343 16-Core Processor)).

cf. the NPS setting in BIOS.

So the default policy seems to be active, and no Ceph NUMA affinity seems to have taken place. Can someone explain me what Ceph (cephadm) is currently doing when the "osd_numa_auto_affinity" config setting is true and NUMA is exposed?

Thanks in advance for any NUMA clue you can give me.

Gr. Stefan

[1]: https://www.youtube.com/watch?v=u8vgo2jfMpo [2]: https://www.reddit.com/r/ceph/comments/15b3rp8/clyso_enterprise_storage_allf... [3]: https://docs.redhat.com/en/documentation/red_hat_openstack_platform/11/html/...

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On Fri, Sep 13, 2024 at 12:16 PM Anthony D'Atri <aad@dreamsnake.net> wrote:

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My sense is that with recent OS and kernel releases (e.g., not CentOS 8) irqbalance does a halfway decent job.

Strongly disagree! Canonical has actually disabled it by default in Ubuntu 24.04 and IIRC Debian already does, too: https://discourse.ubuntu.com/t/ubuntu-24-04-lts-noble-numbat-release-notes/3...

Interesting. The varied viewpoints of the Ceph community are invaluable. Reading the above page, I infer that recent kernels do well by default now?

While irqbalance _can_ do a decent job in some scenarios, it can also really mess things up. For something like Ceph where you are likely running a lot of the same platform(s) and are seeking predictability, you can probably do better controlling affinity yourself. At least, you should be able to do no worse.

Fair enough, would love to

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I came across a recent Ceph day NYC talk from Tyler Stachecki (Bloomberg) [1] and a Reddit post [2]. Apparently there is quita a bit of performance to gain when NUMA is optimally configured for Ceph.

My sense is that NUMA is very much a function of what CPUs one is using, and 1S vs 2S / 4S. With 4S servers I've seen people using multiple NICs, multiple HBAs, etc., effectively partitioning into 4x 1S servers. Why not save yourself hassle and just use 1S to begin with? 4+S-capable CPUs cost more and sometimes lag generationally.

Hey, that's me!

I first saw an elaborate 4S pinning scheme at an OpenStack Summit, 2016 or so.

As Anthony says, YMMV based on your platform, what you use Ceph for (RBD?), and also how much Ceph you're running.

Early versions of Zen had quite bad core to core memory latency when you hopped across CCD/CCX.

There’s a graphic out there comparing those latencies for …. IIRC, Icelake and Rome or Milan.

There's some early warning signs in the Zen 5 client reviews that such latencies may be back to bite (I have not gotten my hands on one yet, nor have I see anyone explain "why" yet):

Ouch. Would one interpret this as Genoa being better?

https://www.anandtech.com/show/21524/the-amd-ryzen-9-9950x-and-ryzen-9-9900x...

In the diagram within that article you can clearly see the ~180ns difference, as well as the "striping" effect, when you cross a CCX. I'm wondering this is a byproduct of the new ladder cache design within the Zen 5 CCX? Regardless: if you have latencies like this within a single socket, you likely stand to gain something by pinning processes to NUMA nodes even with 1P servers. The results mentioned in my presentation are all based on 1P platforms as well for comparison.

Which presentation? I want to read through that carefully. I’m about to deploy a bunch of 1S EPYC 9454 systems with 30TB SSDs for RBD, RGW, and perhaps later CephFS. After clamoring for 1S systems for years I finally got my wish, now I want to optimize them as best I can, especially with 12x 30TB SSDs each (PCI-e Gen 4, QLC and TLC). Bonded 100GE. In the past I inherited scripting that spread HBA and NIC interrupts across physical cores (every other thread) and messed with the CPU governor, but have not dived deeply into NVMe interrupts yet.

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So what is most optimal there? Does it still make sense to have the Ceph processes bound to the CPU where their respective NVMe resides when the network interface card is attached to another CPU / NUMA node? Or would this just result in more inter NUMA traffic (latency) and negate any possible gains that could have been made?

I never benchmarked this, so I can only guess.

However: if you look at /proc/interrupts, you will see that most if not all enterprise NVMes in Linux effectively get allocated a MSI vector per thread per NVMe. Moreover, if you look at /proc/<irq>/smp_affinity for each of those MSI vectors, you will see that they are each pinned to exactly one CPU thread.

In my experience, when NUMA pinning OSDs, only the MSI vectors local to the NUMA node where the OSD runs really have any activity. That seems optimal, so I've never had a reason to look any further.

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So the default policy seems to be active, and no Ceph NUMA affinity seems to have taken place. Can someone explain me what Ceph (cephadm) is currently doing when the "osd_numa_auto_affinity" config setting is true and NUMA is exposed?

I, personally, am in the camp of folk who are not cephadm fans. What I did in my case was to write a shim that sits in front of the ceph-osd@.service unit, effectively overriding the default ExecStart=/usr/bin/ceph-osd.... and replacing it with ExecStart=/usr/local/bin/my_numa_shim /usr/bin/ceph-osd...

The my_numa_shim is a tool which has some apriori knowledge of how the platforms are configured, and makes a decision about which NUMA node to use for a given OSD after probing which NUMA node is most local to the storage device associated with the OSD. It then sets the affinity/memory allocation mode of the process and does an execve to call /usr/bin/ceph-osd as systemd had originally intended. The pinning is not changed by the execve.

Is that tool available?

Would something similar work with cephadm? Probably, but offhand I have no idea how to implement it.

Cheers, Tyler _______________________________________________ ceph-users mailing list -- ceph-users@ceph.io To unsubscribe send an email to ceph-users-leave@ceph.io